Assignment No. 03
Semester: Fall 2011
CS302: Digital Logic Design
Total Marks: 10
Due Date: 27/12/2011
Instructions:
Please read the following instructions carefully before submitting assignment:
It should be clear that your assignment will not get any credit if:
> The assignment is submitted after due date.
> The assignment is submitted via email.
> The submitted assignment does not open or file is corrupt.
> All types of plagiarism are strictly prohibited.
Objectives:
This assignment has been designed to enable you to understand the concepts of:
• SR Latch
• Flip Flops
• Flip-flops with asynchronous inputs
Guidelines:
• Perform/write all steps while solving the problems.
Question No. 1 [Marks: 5]
Complete the table given below for NAND based SR latch. Assume that Q output is initially 1.
EN
S
R
Qt+1
0
1
?
Question No. 2 [Marks: 5]
Determine Q output waveform for a negative edge triggered J-K flip-flop with preset, clear and J, K inputs. You are required to draw Q output waveform using timing diagram.
Deadline:
Your assignment must be uploaded/submitted on or before 27th Dec, 2011
